1. Field of the Invention
The present invention relates to a semiconductor device having an SOI structure and a method of manufacturing the semiconductor device.
2. Description of the Background Art
Attention has recently been paid to a semiconductor device referred to as an SOI (Silicon-On-Insulator) device to be a high-speed device having low power consumption.
The SOI device is fabricated on an SOI substrate having an SOI structure in which a buried oxide film is interposed between an SOI layer and a silicon substrate. In particular, an SOI device in which an SOI layer to be an upper silicon layer has a small thickness (up to approximately several μm) is referred to as a thin film SOI device to which attention has been paid and has been expected for application to an LSI for mobile equipment. Conventionally, an SOI element (a (semiconductor) element formed on an SOI layer having an SOI structure) penetrates through Si (silicon) of the SOI layer and is completely isolated through an oxide film for isolation formed over the buried oxide film.
The complete isolation technique is characterized by latch up free (latch-up is not caused), a resistance to noises and the like because the element is electrically isolated completely from other elements. However, since a transistor is operated in an electrical floating state, there is a problem in that a frequency dependency is caused on a delay time and a floating-body effect, for example, a kink effect in which a hump is generated on a drain current-drain voltage characteristic or the like is produced. In order to suppress the floating-body effect, an isolation oxide film (partial oxide film) is formed in an upper layer portion so as not to come in contact with the buried oxide film and constitutes a partial isolation region together with a part of an SOI layer in a lower layer portion and a body terminal is provided in a body region formed in a region isolated in the partial isolation region. Consequently, a partial isolation technique capable of fixing s substrate potential (body potential) through the SOI layer provided under the partial oxide film is effective. However, there is a problem in that the partial isolation technique does not have the latch up free which is the advantage of the complete isolation technique.
Therefore, there has been developed a partial isolation and complete isolation combination technique having both advantages. In the partial and complete isolation combination technique, trench depths are varied for the partial isolation and complete isolation combination. For this reason, after an oxide film of an isolation oxide film is provided and is then subjected to a CMP processing, dishing is generated in a complete isolation portion having a great trench depth differently from the partial isolation. Accordingly, there is a problem in that the shape of an important isolation edge for the reliability of a gate oxide film is varied between the partial isolation and the complete isolation. In the combination process, moreover, the isolation edge of the complete isolation is lowered so that a threshold voltage of a MOS transistor is locally dropped in an edge portion. Therefore, there is a problem in that a leakage current might be increased.
In only the conventional device, moreover, a distance from the body terminal is varied for each transistor. Therefore, there is a problem in that a body resistance is varied, resulting in a variation in a threshold voltage.
In addition, there is a problem in that a body potential cannot always be fixed with a high stability by the partial isolation technique for fixing the body potential through the SOI layer provided under the partial oxide film.